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VLSIDA

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VLSI Design & Automation Group

UC Santa Cruz VLSI Design and Automation research lab

Santa Cruz, CA
http://vlsida.soe.ucsc.edu
mrg+vlsida@ucsc.edu

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OpenRAM Public

An open-source static random access memory (SRAM) compiler.

Python 340 113
openram-docker-image Public

Shell 4 1
openram-vagrant-image Public

Settings to build a Vagrant image for OpenRAM

Shell 3 2

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All C Dockerfile Python Ruby Shell SourcePawn Verilog

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sky130_fd_bd_sram Public

0 Apache-2.0 0 0 0 Updated Feb 2, 2022
OpenRAM Public
An open-source static random access memory (SRAM) compiler.

Python 340 BSD-3-Clause 113 12 3 Updated Jan 30, 2022
OpenCache Public
An open-source custom cache generator.

Python 2 BSD-3-Clause 0 0 0 Updated Jan 30, 2022
openram_testchip Public
https://caravel-user-project.readthedocs.io

Verilog 2 Apache-2.0 144 0 0 Updated Dec 28, 2021
SKY130_for_KLayout Public
KLayout technology files for Skywater SKY130

Ruby 2 BSD-2-Clause 6 0 0 Updated Dec 16, 2021
sky130_sram_macros Public

SourcePawn 0 Apache-2.0 0 0 0 Updated Dec 14, 2021
skywater-pdk-libs-sky130_fd_pr_reram Public
SKY130 ReRAM and examples (SkyWater Provided)

0 Apache-2.0 6 0 0 Updated Dec 6, 2021
puffery Public
Tools for PUF analysis

Python 4 GPL-3.0 2 0 0 Updated Nov 22, 2021
lithosim Public
This is a very basic lithography simulation and pixel-based OPC tool.

C 4 BSD-3-Clause 2 0 0 Updated Nov 12, 2021
skywater-pdk-libs-sky130_fd_bd_sram Public

0 Apache-2.0 5 0 0 Updated Oct 4, 2021

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