Scala based HDL
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A FPGA friendly 32 bit RISC-V CPU implementation
Assembly 1.4k 250
A basic SpinalHDL project
Scala 36 31
Labs to learn SpinalHDL
Scala 70 23
The sources of the online SpinalHDL doc
Python 11 22
Forked from jijingg/Spinal-bootcamp
SpinalHDL-tutorial based on Jupyter Notebook
Jupyter Notebook 21 7
SpinalHDL - Cryptography libraries
Spike, a RISC-V ISA Simulator
Spen's Official OpenOCD Mirror
CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcrontrollers (MCU).
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