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verilator / verilator

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Remove Warning Message for Variables Only Used as Delays

1

qrqiuren commented Apr 28, 2021

Thanks for taking the time to report this.

What would you like added/supported?

// File: dly_warning.sv

// verilator lint_off ASSIGNDLY

module dly_warning (
    input logic a_in,
    input logic [2:0] delaycw,

    output logic a_out
);

timeunit 1ns;
timeprecision 1ns;

time dly;

assign dly = 5 * delaycw;
assign #dly a_out = a_in;     // Warning ASS

Optimize short Active blocks inline into _eval

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Open

Support pattern member assignment with data type

2

nxbyte / Verilog-Projects

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This repository contains source code for past labs and projects involving FPGA and Verilog based designs

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zeynepCankara / Computer_Organization_Labs

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My solutions for Bilkent University CS224 Computer Organization Labs (Spring 2019). Includes assembly programming assignments together with various processor designs in System Verilog HDL

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