Chisel 3: A Modern Hardware Design Language
Scala 2.3k 405
Rocket Chip Generator
Scala 2.1k 809
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.
C++ 573 110
SweRV EH1 core
SystemVerilog 508 126
Flexible Intermediate Representation for RTL
Scala 490 151
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
C++ 181 37
Output of the sv-tests runs.
Chisel/Firrtl execution engine
Test suite designed to check compliance with the SystemVerilog standard.
Verilator open-source SystemVerilog simulator and lint system
Python interface to FPGA interchange format
