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23 public repositories
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HAL – The Hardware Analyzer
Updated
Oct 19, 2021
VHDL
draws an SVG schematic from a JSON netlist
Updated
Jul 6, 2021
JavaScript
Tools for working with circuits as graphs in python
Updated
Sep 24, 2021
Verilog
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
Updated
Oct 18, 2021
Python
A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).
Updated
Jun 13, 2015
Python
SPICE netlists parser for .NET
This is a demo for still image compression application
Updated
Apr 14, 2018
Verilog
Updated
Dec 3, 2017
ANTLR
Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations
Updated
Jan 22, 2020
SourcePawn
SKiDL Microcontroller Board Wizard
Updated
Mar 25, 2021
Python
This repository contains a python script that converts a Boolean Expression to a .SIM file (circuit netlist description).
Updated
Sep 28, 2020
Python
tile-based digital logic sandbox
Updated
Sep 10, 2021
Python
A low-level hierarchical netlist assembler for FPGAs
Electronic PCB Programmig Language: Create an Electronic Netlist and Schematic using JavaScript and limitless automations.
Updated
Aug 10, 2021
JavaScript
MODNET (MODify NETlist): VHDL/Verilog Fault Injection system
Updated
Jun 27, 2021
Python
Contains VHDL netlists of basic digital circuits.
SUTD 2020 50.002 Computation Structures Code Dump
NetFI-3: Netlist Fault Injection system - Version 3
A few experiments using the SpyDrNet netlist library.
Updated
Mar 31, 2021
Python
A more modular Fluigi Codebase
Updated
Feb 20, 2020
Java
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Together with issue #4, we should write a few tests for making sure refdeses do stay consistent. Something like a copy of servo_micro, and a ton of patches on top of it (all parented to one servo_micro, not on a chain, more like a star). Apply each of those patches then see if refdeses are sticking.
git checkout c718fbc~1 examples/servo_micro.pyfrom google/pcbdl@ba3