An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
C 702 319
The official testing library for Chisel circuits.
Scala 89 39
A Library of Chisel3 Tools for Digital Signal Processing
Scala 144 29
chisel tutorial exercises and answers
Scala 502 170
Simple RISC-V 3-stage Pipeline in Chisel
HAMMER: Highly Agile Masks Made Effortlessly from RTL
Berkeley's Spatial Array Generator
Fork of upstream onnxruntime focused on supporting risc-v accelerators
Wrapper for lowRISC Ibex
Useful utilities for BAR projects
