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vivado

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hdl-util / hdmi

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Open

Translate README.md

sameer commented May 16, 2020

If you speak another language, I would appreciate your help in translating the README.md.

For tables, checklists, or other data that might change, please indicate that that information is in the main README. Otherwise every change to the main README will need to be replicated to the other READMEs.

^ I've tried to do this a bit in the French README. The only thing you need to replicate when

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help wanted good first issue

prjxray

SymbiFlow / prjxray

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Open

Assign xc7 prefix to prjxray tools to avoid conflicts

4

acomodi commented May 25, 2020

All the tools in prjxray should have an xc7 prefix, so to make them unique.

E.g. bitread or bittool could enter in conflicts with other tools names.

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good first issue

Open

Document remaining bits in opentitan bitstream

3

Open

Refactor xjson library

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LeiWang1999 / FPGA

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帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga verilog xilinx vivado pynq

Updated Sep 13, 2021

olofk / edalize

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An abstraction library for interfacing EDA tools

Updated Sep 15, 2021
Python

open-sdr / openwifi-hw

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FPGA/hardware design of openwifi

linux fpga zynq hls verilog xilinx sdr vivado wi-fi analog-devices ieee80211 dma software-defined-radio ofdm csma ad9361 802-11 mac80211 openwifi

Updated Sep 2, 2021
Verilog

pavel-demin / red-pitaya-notes

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Notes on the Red Pitaya Open Source Instrument

radio linux fpga zynq dsp tcl verilog nmr xilinx sdr mca redpitaya vna vivado wspr red-pitaya vitis

Updated Jul 7, 2021
C

changwoolee / lenet5_hls

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FPGA Accelerator for CNN using Vivado HLS

hls accelerator cnn lenet vivado sdx high-level-synthesis sdsoc

Updated Jun 3, 2021
C++

Xilinx / RapidWright

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Build Customized FPGA Implementations for Vivado

fpga xilinx vivado rapidwright

Updated Sep 18, 2021
Java

jofrfu / tinyTPU

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Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Updated Jan 5, 2019
VHDL

tymonx / logic

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CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

cmake asic fpga cpp verification rtl verilog xilinx vivado systemverilog systemc unit-tests hdl modelsim uvm verilator quartus testing-rtl

Updated Nov 25, 2019
SystemVerilog

mshr-h / vscode-verilog-hdl-support

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Verilog HDL/SystemVerilog/Bluespec SystemVerilog support for VS Code

ctags vscode verilog vivado systemverilog icarus-verilog modelsim hacktoberfest verilog-hdl iverilog bluespec-systemverilog verilator language-server-client systemverilog-support svls

Updated Jul 3, 2021
TypeScript

eugene-tarassov / vivado-risc-v

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Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

linux fpga boom xilinx vivado risc-v nexys-video vc707 rocketchip genesys2 kc705

Updated Sep 13, 2021
C

hpcn-uam / Limago

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Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack

verify gui fpga tcp hls vivado network-stack vcu118 alveo-u200 sidler 100gbe alveo-u280

Updated Sep 11, 2021
Tcl

ilaydayaman / CNN_for_SLR

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A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.

fpga cnn verilog vivado slr

Updated Aug 25, 2021
VHDL

Gowtham1729 / Image-Processing

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Image Processing Toolbox in Verilog using Basys3 FPGA

python fpga ram pixel vhdl python3 verilog brightness convolution vivado motion-blur verilog-hdl basys3 hsync basys basys-board coe verilog-project basys3-fpga

Updated Nov 4, 2020
VHDL

capitanov / intfftk

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Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

fpga dsp vhdl verilog fast-fourier-transform xilinx fft vivado altera cooley-tukey-fft digital-signal-processing fast-convolutions radix-2 integer-arithmetic route-optimization

Updated Aug 14, 2020
VHDL

HWAC-DL / hwac_object_tracker

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FPGA accelerated TinyYOLO v2 object detection neural network

fpga detection verilog xilinx vivado pynq tinyyolo

Updated Jul 31, 2018
HTML

nxbyte / ARM-LEGv8

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Verilog Implementation of an ARM LEGv8 CPU

arm verilog xilinx isa vivado hazard-detection ldr pipeline-cpu single-cycle hennessy patterson legv8-arm multi-cycle arm-legv8-simulator forwarding-unit

Updated Oct 3, 2018
Verilog

li3tuo4 / rc-fpga-zcu

Star

Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)

rocket-chip vivado risc-v linux-boot fpga-board zcu102 zynqmp

Updated Jun 14, 2021
Tcl

SymbiFlow / prjuray

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Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.

fpga xilinx vivado fuzzer xilinx-fpga bitstream ultrascale symbiflow ultrascale-plus

Updated Jun 18, 2021
SystemVerilog

tymonx / virtio

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Virtio implementation in SystemVerilog

cmake fpga model rtl verilog xilinx vivado systemverilog systemc hdl virtio verilator quartus

Updated Jan 23, 2018
SystemVerilog

tongplw / HW-Syn-Lab

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⚙Hardware Synthesis Laboratory Using Verilog

hardware verilog xilinx vivado uart vga basys3 hardware-synthesis

Updated May 10, 2020
Verilog

suoglu / Fixed-Floating-Point-Adder-Multiplier

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16-bit Adder Multiplier hardware on Digilent Basys 3

fpga hardware verilog vivado fixed-point floating-point adder multiplier binary16

Updated May 23, 2021
Verilog

Starrynightzyq / Nexys4DDR-ARM-M3-Plate-Recognition

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车牌识别,FPGA,2019全国大学生集成电路创新创业大赛

arm cv vivado nexys4 fpga-cortex-m3

Updated Dec 8, 2019
VHDL

Domipheus / ArtyS7-RPU-SoC

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Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.

c fpga firmware vhdl riscv spi vivado apache2 hdmi fpga-soc risc-v xilinx-vivado dvid riscv32

Updated Oct 5, 2020
VHDL

FloyedShen / mnist_hls

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Lenet for MNIST handwritten digit recognition using Vivado hls tool

zynq hls vivado zedboard fpga-accelerator vivado-hls mnist-hls

Updated Jul 22, 2020
Objective-C

zslwyuan / Hi-DMM

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Hi-DMM: High-Performance Dynamic Memory Management in HLS (High-Level Synthesis)

hls xilinx vivado dynamic-memory-allocation

Updated Oct 30, 2018
VHDL

Goshik92 / SHA256Hasher

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SHA-256 IP core for ZedBoard (Zynq SoC)

arm fpga zynq xilinx sha256 vivado systemverilog soc zedboard

Updated Jun 22, 2018
Verilog

PyFPGA / pyfpga

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Open

Improve the Vivado block design example

rodrigomelo9 opened Feb 11, 2021

enhancement good first issue

Open

Verify windows support

4

sgherbst / svreal

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Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

simulation verilog vcs synthesis vivado systemverilog fixed-point floating-point icarus-verilog iverilog icarus verilator xrun synthesizable xcelium irun ncsim

Updated Jan 13, 2021
SystemVerilog

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