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semiconductor

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dalonsoa
dalonsoa commented May 17, 2020

The documentation for the PDD solver states that the output is provided as a nested dictionary. However, that is not correct: it is provided as a State object with the different keys accesible as attributes. For example:

solar_cell[junction_index]['QE']['EQE']

should be:

solar_cell[junction_index].qe.EQE

[The examples are incorrect](http://docs.solcore.solar

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys).

  • Updated Jul 21, 2020
  • Coq

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