microarchitecture

Open-source high-performance RISC-V processor

A cross platform C99 library to get cpu features at runtime.

Simple yet fancy CPU architecture fetching tool

How to exploit a double free vulnerability in 2021. 'Use After Free for Dummies'

inVtero.net: A high speed (Gbps) Forensics, Memory integrity & assurance. Includes offensive & defensive memory capabilities. Find/Extract processes, hypervisors (including nested) in memory dumps using microarchitechture independent Virtual Machiene Introspection techniques

Achieve peak performance on x86 CPUs and NVIDIA GPUs

Microarchitectural exploitation and other hardware attacks.

A customizable hardware prefetching framework using online reinforcement learning as described in the MICRO 2021 paper by Bera et al. (https://arxiv.org/pdf/2109.12021.pdf).

High performance Bitcoin development platform

A small RISC-V core (SystemVerilog)

FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation

Performance Counter Measurements at the cycle granularity

This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve Hoover

FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64

Sequential entries of a long number with offset for the FPGA microarchitecture on system verilog

One Instruction Set Computer

Custom 64-bit pipelined RISC processor

DSCP is a dynamic secure cache partitioning implementation on gem5. The code includes a ScatterCache (USENIX SECURITY'19) variant and it is partially available to reproduce set partitioning.

Dual-core 16-bit RISC processor

An implementation of the LC-3 architecture in VHDL, as described in the book "Introduction to Computing Systems by P&P".

A small RISC-V core (VHDL)

Virtualization of a 32-bit ARM-like processor with native execution.

[2009 – 2012] MDSP: functional simulation of a Multimedia Digital Signal Processor

.NET version of google/cpu_features to get cpu info at runtime.

This is a repository exclusively created for providing open source verilog codes for various processor microarchitectures and various programming language based codes for research purpose

8-bit MISC processor with pipelining

MIPS Single-Cycle Microarchitecture Processor

A cross platform Redis Module Example that warns and uses the optimized functions based on instruction set extensions available and or microarchitecture