SCR1 is a high-quality open-source RISC-V MCU core in Verilog
SystemVerilog 519 185
open-source SDKs for the SCR1 core
C 54 28
SoftFloat release 3
Simple c++11 demo of "Dining philosophers problem"
OpenOCD Syntacore targets
Syntacore first stage bootloader
FPGA-based SDK projects for SCRx cores
Working draft of the proposed RISC-V V vector extension
RISC-V port of GDB
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