CHIPS Alliance

Surelog Public
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

C++ 208 Apache-2.0 45 51 (3 issues need help) 0 Updated Apr 8, 2022
firrtl Public
Flexible Intermediate Representation for RTL

Scala 520 Apache-2.0 157 168 (2 issues need help) 88 Updated Apr 8, 2022
f4pga Public
Documentation for F4PGA

Makefile 60 Apache-2.0 20 8 3 Updated Apr 8, 2022
sv-tests Public
Test suite designed to check compliance with the SystemVerilog standard.

SystemVerilog 158 ISC 46 38 (5 issues need help) 23 Updated Apr 7, 2022
verible Public
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.

C++ 624 Apache-2.0 121 278 (15 issues need help) 13 Updated Apr 7, 2022
f4pga-examples Public
Example designs showing different ways to use F4PGA toolchains.

Verilog 181 Apache-2.0 55 86 14 Updated Apr 7, 2022
cde Public
A Scala library for Context-Dependent Evironments

Scala 16 Apache-2.0 15 1 1 Updated Apr 7, 2022
chisel3 Public
Chisel 3: A Modern Hardware Design Language

Scala 2,473 Apache-2.0 438 203 (1 issue needs help) 90 Updated Apr 7, 2022
yosys-f4pga-plugins Public
Plugins for Yosys developed as part of the F4PGA project.

Verilog 28 Apache-2.0 26 30 6 Updated Apr 7, 2022
UHDM Public
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

C++ 97 Apache-2.0 28 15 1 Updated Apr 7, 2022

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