good first issue
An issue whose fix is simple. Perfect for a new developer wanting to get involved!
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chisel
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Open
V extension support
siyy123
commented
Apr 5, 2021
Type of issue: feature request
Impact: new rtl
Development Phase: request
Other information
As the vector extension proposal is near stable and the necessary things is defined in the rocket chip repo I think now the vector e
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
boom
rocket
rocket-chip
chip-generator
chisel
riscv
rtl
peripherals
soc
out-of-order
superscalar
risc-v
firesim
accelerators
chipyard
hwacha
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Updated
Apr 8, 2022 - C
LogicalError
commented
Sep 23, 2020
See title.
Hardest part is probably icon design, and where to place it
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
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Updated
Jan 23, 2020 - Scala
proppy
commented
Aug 3, 2021
It would be nice if the Hardware Description Languages section mentioned simulating tooling like:
- iverilog
- gtkwave
- verilator
A few things that I wish I learned from the workshop rather that "discovering/googling" by myself:
- use iverilog as a linter (seems to be more pedantic that yosys).
- how to create testbench
- how to
$monitorvariable - gotcha to create / optimize vhd fi
documentation
Improvements or additions to documentation
enhancement
New feature or request
help wanted
Extra attention is needed
good first issue
Good for newcomers
The official testing library for Chisel circuits.
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Updated
Apr 7, 2022 - Scala
Provides dot visualizations of chisel/firrtl circuits
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Updated
Mar 15, 2022 - Scala
A dynamic verification library for Chisel.
testing
coverage
scala
verification
chisel
constrained-random-verification
functional-coverage
bus-functional-model
chisel-test
timed-assertions
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Updated
Mar 21, 2022 - Scala
A fault-injection framework using Chisel and FIRRTL
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Updated
Sep 4, 2018 - Scala
Quasar 2.0: Chisel equivalent of SweRV-EL2
scala
processor
chisel
riscv
rtl
chisel3
open-source-hardware
verilator
asic-verification
axi4
ahb-lite
asic-design
swerv
swerv-el2
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Updated
Apr 13, 2021 - Scala
A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain( chisel, mill, verilator, NEMU, AM and difftest framework). And the last three items are from the NJU-ProjectN.
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Updated
Mar 21, 2022 - Scala
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It's a source of confusion when to use Decoupled and when to use DecoupledI