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risc

Here are 189 public repositories matching this topic...

Ripes

mortbopet / Ripes

Sponsor

Open

Add ISA simulator processor model

mortbopet commented Apr 1, 2022

For those who want the fastest possible simulation, and do not care about any form of datapath visualization, there should be an option to select an ISA simulator processor model.

This processor model, while complying with the ProcessorInterface, will in VSRTL be implemented as a "black box" - in other words, pure C++ logic.

Read more

good first issue

Open

Add a pseudoinstructions test suite

Open

Add counters to see the number of stalls and flushes during the code execution

6

Find more good first issues

chipsalliance / Cores-SweRV

SweRV EH1 core

fpga processor riscv rtl risc risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design swerv swerv-eh1

Updated Jan 27, 2022
SystemVerilog

jupiter

andrescv / jupiter

RISC-V Assembler and Runtime Simulator

education simulator assembler riscv risc risc-v riscv-asm rv32 rv32imf riscv-simulator runtime-simulator

Updated Nov 25, 2021
Java

mipt-mips

MIPT-ILab / mipt-mips

Open

Adopt Clang-Format

pavelkryukov commented Feb 13, 2022

Clang-Format is a tool to format code automatically according to some guidelines.

Your objectives are:

define .clang-format file for our project, reflecting our guidelines
apply the guidelines automatically to our flow
implement a [Git hook](https://git-scm

Read more

infrastructure 4 good first issue S1 — Infrastructure

Open

Verify correctness of read-after-write behavior

Open

Implement RV64 bit manipulation instructions on 32-bit registers

Find more good first issues

LekKit / RVVM

The RISC-V Virtual Machine

Updated May 28, 2022
C

Wren6991 / RISCBoy

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

cpu fpga gameboy pcb risc risc-v

Updated Oct 9, 2021
C

kvakil / venus

RISC-V instruction set simulator built for education

education frontend backend assembler risc risc-v venus

Updated Apr 2, 2022
Kotlin

Vulcan

vmmc2 / Vulcan

RISC-V Instruction Set Simulator (Built for education).

education simulator assembly computer-architecture risc risc-v

Updated Jan 24, 2022
Dart

mrisc32

mrisc32 / mrisc32

MRSIC32 ISA documentation and development

cpu isa risc mrisc32

Updated Mar 23, 2022
TeX

Mariotti94 / WebRISC-V

WebRISC-V: A Web-Based Education-Oriented RISC-V Pipeline Simulation Environment [PHP]

php education processor-architecture simulator pipeline assembly computer-architecture risc risc-v pipeline-simulation-environment

Updated Apr 4, 2022
PHP

liuqidev / 8-bits-RISC-CPU-Verilog

Architecture and Verilog Implementation of 8-bits RISC CPU based on FSM. 基于有限状态机的8位RISC（精简指令集）CPU（中央处理器）简单结构和Verilog实现。

cpu fsm verilog risc

Updated Jan 20, 2019
Verilog

lxp32 / lxp32-cpu

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

cpu fpga x86-64 vhdl riscv x86 risc risc-v wishbone soft-core risc-processor wishbone-bus risc-cpu

Updated Oct 21, 2021
Assembly

mikeroyal / RISC-V-Guide

RISC-V Guide

open-source awesome embedded fpga architecture intel embedded-systems riscv awesome-list hardware-designs computer-architecture risc risc-v risc-processor sifive riscv64 riscv-simulator riscv-emulator riscv-assembly

Updated May 12, 2022
Assembly

michaeljclark / riscv-meta

RISC-V Instruction Set Metadata

metadata riscv risc risc-v

Updated Oct 21, 2018

wel97459 / FPGACosmacELF

A re-creation of a Cosmac ELF computer, Coded in SpinalHDL

cpu fpga processor fred risc rca 8bit spinalhdl cosmac cosmac-elf

Updated Apr 23, 2021
VHDL

SuperJMN / Plotty

Sponsor

C language compiler from scratch for a custom architecture, with virtual machine and all

c emulator parser csharp parsing compiler uwp virtual-machine net risc c-language superpower

Updated May 13, 2018
C#

ustb-owl / Uranus

Uranus MIPS processor by MaxXing & USTB NSCSCC team

cpu fpga mips verilog risc

Updated Dec 14, 2019
Verilog

platformio / platform-shakti

Shakti: development platform for PlatformIO

platformio riscv risc risc-v platformio-platform

Updated May 28, 2022
Python

bitmario / RISVM

A low overhead, embeddable bytecode virtual machine in C++

vm interpreter bytecode cpp virtual-machine asm assembler risc bytecode-interpreter

Updated Dec 25, 2018
C++

mrisc32 / mrisc32-a1

A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA

cpu vhdl risc soft-core fpu mrisc32

Updated May 1, 2022
VHDL

Internet2-WG / rust-aluvm

Open

Do a test coverage

3

dr-orlovsky opened Jun 29, 2021

good first issue help wanted *security* epic

ulx3s / ulx3s.github.io

community projects that can be used with the ULX3S FPGA ESP32 board

fpga vhdl verilog risc ecp5 ulx3s emard

Updated Oct 3, 2021

oberon

fzipp / oberon

Project Oberon RISC emulator in Go

go emulator golang oberon risc oberon-system oberon-07 wirth wirth-oberon project-oberon

Updated May 12, 2022
Go

rv-link

michahoiting / rv-link

RV-Link: In application debugger for RISC-V micro-controllers, RISC-V emulator, running on RISC-V development boards (e.g. Sipeed Longan Nano or GD32VF103C-START).

c microcontrollers platformio risc jtag dongle jtag-probe longan-nano gd32vf103 rv-link

Updated Feb 10, 2021
C

ben-marshall / croyde-riscv

A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.

cryptography microcontroller cpu crypto verilog mit-license systemverilog risc formal-verification yosys risc-v verilator micro-controller riscv64

Updated Jan 31, 2022
SystemVerilog

pleasewhy / startos

rewrite subset of linux 2.6 by OOP, C++ advanced topics

Updated Jul 22, 2021
Assembly

lite-david / comet

RISC-V ISA based 32-bit processor written in HLS

asic fpga hls comet isa vivado risc catapult

Updated Nov 7, 2019
C

pmetras / nim0

Nim0 is a toy compiler for a limited subset of Nim language, all in 5 heavily documented source files so that you can understand them. It is a port of Niklaus Wirth's Oberon-0 compiler.

emulator nim compiler toy-language risc oberon0

Updated Apr 27, 2021
Nim

BigEd / XSOC-xr16

System-on-a-Chip for FPGA, with xr16 RISC core and LCC port

cpu fpga risc system-on-chip 16bit non-commercial-license revocable-license

Updated Jul 23, 2017
C

spider-tronix / VLSI

RISC V core implementation using Verilog.

cpu fpga processor computer-architecture risc verilog-hdl risc-v

Updated Mar 27, 2021
Verilog

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