#
skywater
Here are 10 public repositories matching this topic...
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
magic
asic
rtl
verilog
systemverilog
vlsi
foundry
fault
yosys
klayout
caravel
netgen
system-on-chip
openroad
openram
skywater
130nm
soc-design
rtl2gds
qflow
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Updated
May 31, 2022 - Verilog
Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
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Updated
Mar 26, 2022 - Verilog
GitHub Actions for usage with Google's 130nm manufacturable PDK for SkyWater Technology found @ https://github.com/google/skywater-pdk
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Updated
Jun 3, 2021 - Python
designed a simple D-flipflop from JK-flipflop using eSIM and SKY130nm pdk
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Updated
Jul 11, 2021
Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process
magic
asic
wavelet
audio-processing
mixed-signal
integrated-circuits
cochlea
skywater
mixed-signal-chips
130nm
switched-capacitor
xschem
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Updated
Dec 31, 2021 - Tcl
Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process, embedded in efabless Caravel
audio
magic
asic
wavelet
audio-processing
mixed-signal
netgen
integrated-circuits
cochlea
skywater
130nm
switched-capacitor
caravel-shuttle
xshem
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Updated
May 31, 2022 - Verilog
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