The CHIPS Alliance develops high-quality, open source hardware designs relevant to silicon devices and FPGAs.
The CHIPS Alliance hosts multiple open source "projects", similar projects are organized into Workgroups.
| Workgroup |  Primary Repos |
Description | |
|---|---|---|---|
| Analog | The Analog workgroup works on open source Analog/Mixed-Signal design and verification. | ||
| Chisel |
chisel3 firrtl |
 The Chisel Workgroup is formed around the eponymous hardware design language (HDL) but also includes FIRRTL and tools such as Treadle. |
|
| Cores | Cores-SweRV |
The cores working group is currently not operating. | |
| F4PGA |
f4pga f4pga-examples fasm |
 The F4PGA Workgroup was formed to drive open source tooling, IP cores and research for FPGA devices. |
|
| Interconnects | The Interconnects Workgroup focuses on OmniXtend and the AIB Chiplet standard. | ||
| Rocket | rocket-chip |
The Rocket Chip Workgroup covers the “Rocket” RISC-V core generator as well as TileLink. | |
| Tools | The Tools Workgroup of CHIPS Alliance covers a wide array of open source tooling for ASIC and FPGA design, mostly focusing around digital design. There are a number of subgroups of the Tools working group. | ||
| • RISC-V DV | riscv-dv |
Workgroup is concerned with the development of the RISC-V DV framework and related technologies. | |
| • SystemVerilog | sv-tests verible Surelog |
Gathers projects related to the SystemVerilog (SV) Hardware Description Language (HDL). |
