Here are
76 public repositories
matching this topic...
Open-source high-performance RISC-V processor
Updated
Mar 6, 2022
Scala
Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
Updated
Jun 25, 2020
Scala
Provides dot visualizations of chisel/firrtl circuits
Updated
Feb 8, 2022
Scala
educational microarchitectures for risc-v isa
Updated
Feb 18, 2019
Scala
The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.
Updated
Mar 6, 2022
JavaScript
Updated
Mar 2, 2022
Scala
vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
Updated
Apr 6, 2020
Scala
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
Updated
Apr 11, 2021
Scala
Lectures for the Agile Hardware Design course in Jupyter Notebooks
Updated
Mar 4, 2022
Jupyter Notebook
Updated
Jul 1, 2020
Scala
Quasar 2.0: Chisel equivalent of SweRV-EL2
Updated
Apr 13, 2021
Scala
PYNQ with Chisel and Rust
An SoC with multiple RISC-V IMA processors.
Updated
Aug 1, 2018
Scala
Chisel library for Unum Type-III Posit Arithmetic
Updated
Jul 2, 2020
Scala
Learning how to make RISC-V 32bit CPU with Chisel
Updated
Sep 17, 2021
Scala
Systolic-array based Deep Learning Accelerator generator
Updated
Dec 11, 2020
Verilog
『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ
Updated
Jul 30, 2019
Scala
A caravan equipped with API for creating bus protocols in Chisel with ease.
Updated
Jul 13, 2021
Scala
BFM Tester for Chisel HDL
Updated
Nov 27, 2021
Scala
A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
Updated
Jul 14, 2021
Verilog
A soft multimedia/graphics processor prototype in Chisel 3
Updated
Mar 6, 2022
Scala
ハードウェア構築言語Chiselでちょっとしたコードを書き溜めておくプロジェクト
A Scala w/ Chisel based implementation of a processing engine generator for neural network accelerators.
Updated
Aug 16, 2018
Jupyter Notebook
Chisel3 implementation of IEEE-754 compliant floating point data type (logic & representation)
Updated
Dec 16, 2019
Scala
Chisel3 AXI4-{Lite, Full, Stream} Definitions
Updated
Dec 31, 2018
Scala
Updated
Jan 9, 2021
Scala
Various examples for Chisel HDL
A configurable processing element for deep neural network accelerators
Updated
Sep 22, 2018
Scala
Improve this page
Add a description, image, and links to the
chisel3
topic page so that developers can more easily learn about it.
Curate this topic
Add this topic to your repo
To associate your repository with the
chisel3
topic, visit your repo's landing page and select "manage topics."
Learn more
You can’t perform that action at this time.
You signed in with another tab or window. Reload to refresh your session.
You signed out in another tab or window. Reload to refresh your session.
Type of issue: documentation