Here are
18 public repositories
matching this topic...
A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
🤖 SoCFPGA: Open-Source Embedded Linux Distribution with a highly flexible build system, developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)
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Oct 18, 2021
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Python
SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)
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Jun 9, 2021
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Verilog
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Sep 15, 2021
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Python
IntelFPGA configuration & Avalon-MM access library for FlashAir
Yocto Project BSP meta-layer for Intel (ALTERA) SoC-FPGAs (SoCFPGA) - with step by step guide
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Dec 30, 2021
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BitBake
High-Level Synthesis with Partial Evaluation
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Jan 18, 2022
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CMake
Demonstration how to build a Management Web interface to interact with the FPGA fabric and change the FPGA configuration with the Django Framework
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Jun 27, 2021
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Python
Automatically create a NIOS II Eclipse Project with the latest FreeRTOS Version, the Intel hwlib and more...
Script to build the bootloader (u-boot) and bring all components to a bootable image for Intel (ALTERA) SoC-FPGAs
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Oct 27, 2021
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Python
A Comprehensive Dataflow Compiler for High-Level Synthesis
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Apr 11, 2022
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CMake
Source Code of Yocto Layer for accessing FPGA Manager of the Intel (ALTERA) Cyclone V SoCFPGA
Source Code of Yocto Layer for accessing FPGA Manager of the Intel (ALTERA) Arria 10 SX SoCFPGA
Fletcher Open Programmable Acceleration Engine platform support
Serving object detection models on different hardware.
OpenCL wrapper for Intel's unique chip ID function built for the Cyclone V chip on the DE1-SoC board
Play and learn with the Terasic DE0-Atlas/Nano-SoC Kit featuring a Altera/Intel Cyclone V 5CSEMA4U23C6N FPGA with integrated dual-core ARM Cortex-A9.
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Sep 6, 2019
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Verilog
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