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chipyard

Here are 7 public repositories matching this topic...

ucb-bar / chipyard

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

boom rocket rocket-chip chip-generator chisel riscv rtl peripherals soc out-of-order superscalar risc-v firesim accelerators chipyard hwacha

Updated Feb 16, 2022
C

firesim / FireMarshal

Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.

linux fedora spike distro qemu buildroot workload firesim chipyard

Updated Feb 15, 2022
Python

MaxXSoft / Bossa

BOOM's Simulation Accelerator.

simulation accelerator boom rocket rocket-chip chisel riscv rtl firrtl soc risc-v verilator chipyard

Updated Dec 16, 2021
Scala

Fleker / chipyard-viewer

Open

Assembly instruction decoder

3

Fleker commented Sep 26, 2021

Have a mapping from the assembly op to the canonical instruction.

addi ...

Should be mapped to some kind of content like:

Add Immediate: This instruction is used to do X, Y, or Z.

Read more

enhancement good first issue hacktoberfest

ThePituLegend / RISC-V_DE10-Nano

This project aims to boot Linux on a RocektChip based SoC, synthesised on the DE10-Nano board. Computer Science Bachelor's Thesis at UAB, Spain.

fpga riscv altera ucberkeley risc-v altera-fpga riscv-asm de10-nano riscv64 terasic rocketchip riscv-assembly chipyard

Updated Feb 7, 2022
Verilog

Kian75 / Chisel_Examples

fpga rtl chisel3 risc-v chipyard

Updated Aug 1, 2021
Scala

RedFlag2017 / rocket-soc-tb

A systemverilog/UVM/Makefile testbench for Rocket RISC-V SoCs

soc risc-v chipyard testbech verifcation

Updated Jun 19, 2020
Verilog

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