Type:Enhancement
Feature requests, enhancements
Good First Issue
Good issue to work on for newcomers
Component:Tool-and-Build
Tool and build system related issues
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cpucore
Here are 3 public repositories matching this topic...
i8080 precise replica in Verilog, based on reverse engineering of real die
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Updated
Jul 13, 2019 - Verilog
Revengineered ancient PDP-11 CPUs, originals and clones
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Updated
Feb 19, 2022 - Verilog
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To help users identify how their Verilator simulation of Ibex was built it would be nice to display the parameters (or name of the configuration) that were chosen when running the simulation -- either by default, or as part of a config parameter (e.g.
--version).The parameter values should be available from Verilator at runtime, so we probably don't need any compile-time magic to pass them i