#
asic
Here are 177 public repositories matching this topic...
Component:RTL
For issues in the RTL (e.g. for files in the rtl directory)
Good First Issue
Good first issue to work on if you want to contribute
Haskell to VHDL/Verilog/SystemVerilog compiler
-
Updated
May 3, 2022 - Haskell
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
magic
asic
rtl
verilog
systemverilog
vlsi
foundry
fault
yosys
klayout
caravel
netgen
system-on-chip
openroad
openram
skywater
130nm
soc-design
rtl2gds
qflow
-
Updated
May 3, 2022 - Verilog
Digital Signature Service : creation, extension and validation of advanced electronic signatures
-
Updated
Apr 11, 2022 - Java
curiousengineer
commented
Dec 1, 2020
Here is the problem:
$ make compile
Traceback (most recent call last):
File "C:\My_Designs\probe_fpga_design_1\run.py", line 336, in
main()
File "C:\My_Designs\probe_fpga_design_1\run.py", line 181, in main
vu.add_osvvm()
File "c:\my_designs\probe_fpga_design_1\deps\vunit\vunit\ui_init_.py", line 1030, in add_osvvm
self.builtins.add("osvvm")
File "c:\my
collection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning
compression
asic
university
fpga
deep-learning
neural-network
stanford-university
harvard-university
-
Updated
Apr 11, 2019
RISC-V CPU Core (RV32IM)
-
Updated
Sep 18, 2021 - Verilog
Open
Add AXI FIFO
andreaskurth
commented
Dec 8, 2021
We have axi_cut and axi_multicut for pipelining (to be unified), but we currently don't have a module for buffering AXI beats in FIFOs. This gap can be filled by a new axi_fifo module.
Implementing thi
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
python
infrastructure
asic
fpga
simulation
vhdl
verification
xilinx
synthesis
regression-testing
altera
hardware-designs
lattice
hardware-libraries
poc-library
vlsi
testbenches
hardware-modules
osvvm
uvvm
vunit
-
Updated
Nov 29, 2020 - VHDL
32-bit Superscalar RISC-V CPU
linux
asic
cpu
fpga
verilog
xilinx
superscalar
in-order
risc-v
branch-prediction
coremark
rv32i
verilator
riscv-linux
rv32im
artix-7
pipelined-processors
-
Updated
Sep 18, 2021 - Verilog
Reverse-engineered schematics for DMG-CPU-B
-
Updated
Nov 30, 2020
A-RK6
commented
Jan 10, 2018
Broadening the horizons of the Antminer-Monitor-Master App makes perfect sense now that GPU mining is becoming more and more popular.
At present, EthOS have over 50,000 miners working with their OS so their software is well developed and regularly maintained.
An example of the EthOS monitor can be found here: 48061f.ethosdistro.com
Example API:
{"rigs":{"91c5eb":{"condition":"high_lo
Open
Control
12
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
cmake
asic
fpga
cpp
verification
rtl
verilog
xilinx
vivado
systemverilog
systemc
unit-tests
hdl
modelsim
uvm
verilator
quartus
testing-rtl
-
Updated
Nov 25, 2019 - SystemVerilog
Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
-
Updated
Mar 10, 2022 - Verilog
Open source machine learning accelerators
-
Updated
May 3, 2022 - Scala
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
-
Updated
Oct 22, 2021 - Verilog
SystemRDL 2.0 language compiler front-end
asic
fpga
eda
registers
register-descriptions
systemrdl-compiler
hardware-description-language
design-automation
register-description-language
-
Updated
Apr 17, 2022 - C++
Code generation tool for configuration and status registers
asic
fpga
vhdl
eda
rtl
verilog
csr
systemverilog
soc
uvm
ral
axi
amba
apb
register-descriptions
wishbone-bus
uvm-ral-model
uvm-register-model
wiki-documents
-
Updated
Apr 12, 2022 - Ruby
8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
asic
ic
intellectual-property
pll
analog-circuit
rtl2gds
clock-multiplier
phase-detector
charge-pump
manufacturable
-
Updated
Jul 31, 2021
Awesome ASIC design verification
-
Updated
Feb 9, 2022
Improve this page
Add a description, image, and links to the asic topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the asic topic, visit your repo's landing page and select "manage topics."
If this is not the case a page fault should be generated. Right now we generate an instruction access fault.
https://github.com/pulp-platform/ariane/blob/ad70ce1f30dad539e5a365ffe71a02aaf20b397e/src/load_store_unit.sv#L339