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Jul 18, 2022 - Haskell
systemverilog
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Translate README.md
Test case
typedef dv_base_env_cov #(.CFG_T(tl_agent_env_cfg)) tl_agent_env_cov;Actual output
typedef dv_base_env_cov#(.CFG_T(tl_agent_env_cfg)) tl_agent_env_cov;Expected or suggested output (original formatting)
typedef dv_base_env_cov #(.CFG_T(tl_agent_env_cfg)) tl_agent_env_cov;Verible version:
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Jul 7, 2020 - SystemVerilog
Add AXI FIFO
We have axi_cut and axi_multicut for pipelining (to be unified), but we currently don't have a module for buffering AXI beats in FIFOs. This gap can be filled by a new axi_fifo module.
Implementing thi
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When running the regression, the resulting logs seem to end up in third_party/tests/$TEST/.... This of course is not unnoticed by git, so a git status shows a ton of non-added new files added.
To reproduce:
make
make regression
git status # observe all the filesBuild or test artifacts should never clutter the rest of the code-base (we should regard them as read-only in
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Jul 2, 2022 - Python
With VCS (which is picky regarding LRM SystemVerilog), I get the following compilation error
“ Following verilog source has syntax error :
Select on function call uvma_rvfi_instr_mon.sv
token is ']'
mon_trn.csrs["dcsr"].get_csr_retirement_data()[3]);
file with the syntaxe error is at: https://github.com/openhwgroup/core-v-verif/blob/master/lib/uvm_agents/uvma_rvfi/uvma_rvfi_instr_mon.sv.
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Nov 25, 2019 - SystemVerilog
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Here are some "nice to have" feature requests for the cool new "Compared test results" output that has been recently added.
- Colors! It would be nice to highlight;
- Improvements in green
- Regressions in red.
- Non-changes de-emphasized in light grey.
- Link to the published version of the before and after results so people can understand exactly
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Jul 18, 2022 - SystemVerilog
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Oct 22, 2021 - Verilog
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Mar 3, 2022 - Python
- AxCache[0]
- 0: Non-bufferable
- 1: Bufferable
- AxCache[1]
- 0: Non-modifiable
- 1: Modifiable
- AxCache[2]
- 0: No Read-allocate
- 1: Read-allocate
- AxCache[3]
- 0: No Write-allocate
- 1: Write-allocate
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Jul 5, 2022 - Ruby
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Apr 17, 2022 - SystemVerilog
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Jul 16, 2022 - C++
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If you speak another language, I would appreciate your help in translating the
README.md.For tables, checklists, or other data that might change, please indicate that that information is in the main README. Otherwise every change to the main README will need to be replicated to the other READMEs.
^ I've tried to do this a bit in the French README. The only thing you need to replicate when