efabless

Pinned

1. caravel_user_project Public template

   https://caravel-user-project.readthedocs.io

   Verilog 59 185

2. caravel_user_project_analog Public template

   Verilog 15 64

3. mpw_precheck Public

   Python 23 18

4. caravel Public

   Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

   Verilog 56 18

5. caravel_mgmt_soc_litex Public

   https://caravel-mgmt-soc-litex.readthedocs.io/en/latest/

   Verilog 13 9

6. skywater-pdk-central Public

   37 5