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Pinned

  1. MIPS_Multi_Implementation Public

    MIPS Single Cycle/Multi Cyle/5-Stage Pipeline Verilog Implementation

    Verilog

  2. apb_gpio_uvm_verification Public

    using uvm register model

  3. pss_verification Public

    Verilog

525 contributions in the last year

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Contribution activity

July 2022

Created 16 commits in 3 repositories
Created 2 repositories
7 contributions in private repositories Jul 3 – Jul 21

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