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vivado

Here are 385 public repositories matching this topic...

LeiWang1999 / FPGA

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga verilog xilinx vivado pynq

Updated May 15, 2022

hdl-util / hdmi

Send video/audio over HDMI on an FPGA

audio video fpga intel xilinx vivado altera hdmi systemverilog dvi quartus hdlmake

Updated Dec 17, 2022
SystemVerilog

fastmachinelearning / hls4ml

Machine learning on FPGAs using HLS

python machine-learning fpga hls keras pytorch vivado vivado-hls onnx

Updated Dec 23, 2022
C++

prjxray

f4pga / prjxray

Documenting the Xilinx 7-series bit-stream format.

toolchain tools fpga xilinx vivado fuzzer xilinx-fpga bitstream artix7 artix kintex7 symbiflow

Updated Dec 24, 2022
Python

olofk / edalize

An abstraction library for interfacing EDA tools

Updated Dec 26, 2022
Python

eugene-tarassov / vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

linux fpga boom riscv xilinx vivado risc-v nexys-video vc707 rocketchip genesys2 kc705 arty-a7

Updated Dec 16, 2022
C

pavel-demin / red-pitaya-notes

Notes on the Red Pitaya Open Source Instrument

radio linux fpga zynq dsp tcl verilog nmr xilinx sdr mca redpitaya vna vivado wspr red-pitaya vitis

Updated Nov 16, 2022
C

jofrfu / tinyTPU

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

Updated Jan 5, 2019
VHDL

changwoolee / lenet5_hls

FPGA Accelerator for CNN using Vivado HLS

hls accelerator cnn lenet vivado sdx high-level-synthesis sdsoc

Updated Oct 25, 2021
C++

tymonx / logic

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

cmake asic fpga cpp verification rtl verilog xilinx vivado systemverilog systemc unit-tests hdl modelsim uvm verilator quartus testing-rtl

Updated Nov 25, 2019
SystemVerilog

Xilinx / RapidWright

Build Customized FPGA Implementations for Vivado

fpga xilinx vivado rapidwright

Updated Dec 20, 2022
Java

mshr-h / vscode-verilog-hdl-support

Sponsor

HDL support for VS Code

ctags vscode verilog vivado systemverilog icarus-verilog modelsim hacktoberfest verilog-hdl iverilog bluespec-systemverilog verilator language-server-client systemverilog-support svls

Updated Dec 28, 2022
TypeScript

hpcn-uam / Limago

Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack

fpga tcp hls vivado network-stack vcu118 alveo-u200 100gbe alveo-u280

Updated Sep 11, 2021
Tcl

Gowtham1729 / Image-Processing

Image Processing Toolbox in Verilog using Basys3 FPGA

python fpga ram pixel vhdl python3 verilog brightness convolution vivado motion-blur verilog-hdl basys3 hsync basys basys-board coe verilog-project basys3-fpga

Updated Aug 17, 2022
VHDL

UCLA-VAST / RapidStream

[FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.

fpga hls routing parallel dataflow vivado placement

Updated Dec 20, 2022
Python

nxbyte / ARM-LEGv8

Verilog Implementation of an ARM LEGv8 CPU

arm verilog xilinx isa vivado hazard-detection ldr pipeline-cpu single-cycle hennessy patterson legv8-arm multi-cycle arm-legv8-simulator forwarding-unit

Updated Oct 3, 2018
Verilog

Starrynightzyq / Nexys4DDR-ARM-M3-Plate-Recognition

车牌识别,FPGA,2019全国大学生集成电路创新创业大赛

arm cv vivado nexys4 fpga-cortex-m3

Updated Dec 8, 2019
VHDL

ilaydayaman / CNN_for_SLR

A trained Convolutional Neural Network implemented on ZedBoard Zynq-7000 FPGA.

fpga cnn verilog vivado slr

Updated Jul 12, 2022
Verilog

hukenovs / intfftk

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

fpga dsp vhdl verilog fast-fourier-transform xilinx fft vivado altera cooley-tukey-fft digital-signal-processing fast-convolutions radix-2 integer-arithmetic route-optimization

Updated Jul 5, 2022
VHDL

HWAC-DL / hwac_object_tracker

FPGA accelerated TinyYOLO v2 object detection neural network

fpga detection verilog xilinx vivado pynq tinyyolo

Updated Jul 31, 2018
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