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darkriscv Public

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Verilog 1.6k 244

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darkriscv Public
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Verilog 1,581 BSD-3-Clause 244 13 1 Updated Dec 29, 2022

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