ghdl

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Here are 61 public repositories matching this topic...

ghdl / ghdl

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VHDL 2008/93/87 simulator

simulator compiler hardware llvm vhdl gcc ghdl hacktoberfest testbench

Updated Mar 28, 2023
VHDL

olofk / edalize

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An abstraction library for interfacing EDA tools

Updated Mar 28, 2023
Python

suoto / hdl_checker

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Repurposing existing HDL tools to help writing better code

Updated Jan 28, 2023
Python

jakubcabal / spi-fpga

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SPI master and SPI slave for FPGA written in VHDL

fpga controller vhdl accelerometer spi ghdl spi-master spi-slave cyc1000 spi-loopback spi-controller

Updated Apr 24, 2021
VHDL

jakubcabal / uart-for-fpga

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Simple UART controller for FPGA written in VHDL

fpga simulation controller vhdl uart ghdl wishbone uart-controller wishbone-bus cyc1000 uart-loopback

Updated Aug 7, 2021
VHDL

Paebbels / JSON-for-VHDL

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A JSON library implemented in VHDL.

parser json fpga simulation vhdl xilinx synthesis lattice fileformat modelsim questasim ghdl

Updated Sep 5, 2022
VHDL

tmeissner / psl_with_ghdl

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Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

vhdl assertions ghdl formal-verification yosys psl symbiyosys functional-coverage

Updated Jan 30, 2023
VHDL

PyFPGA / pyfpga

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A Python package to use FPGA development tools programmatically.

Updated Jan 31, 2023
Python

tmeissner / cryptocores

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cryptography ip-cores in vhdl / verilog

cryptography fpga vhdl verilog testbenches ghdl

Updated Feb 20, 2021
VHDL

tmeissner / formal_hw_verification

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Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog systemverilog ghdl formal-verification yosys psl symbiyosys

Updated Oct 5, 2021
VHDL

dbhi / vboard

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Virtual development board for HDL design

vhdl verilog hdl ghdl cosim vpi verilator fli vhpidirect

Updated Apr 25, 2022
VHDL

ghdl / docker

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Scripts to build and use docker images including GHDL

dockerfiles hardware ci simulation vhdl actions verilog synthesis icestorm gtkwave ghdl testbench vunit yosys openocd pnr nextpnr prjtrellis

Updated Feb 26, 2023
Shell

stnolting / neorv32-setups

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📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

fpga vhdl intel verilog xilinx lattice soc ghdl yosys risc-v neorv32

Updated Mar 27, 2023
VHDL

stnolting / neorv32-verilog

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♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

asic fpga verilog icarus-verilog ghdl neorv32

Updated Mar 27, 2023
Verilog

tmeissner / libvhdl

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Library of reusable VHDL components

coverage fpga vhdl verification assertions testbenches ghdl formal-verification osvvm psl

Updated May 20, 2022
VHDL

stnolting / neorv32-riscof

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✔️Port of RISCOF to verify the NEORV32 Processor's RISC-V ISA compatibility.

processor vhdl verification riscv isa ghdl risc-v neorv32 riscof sail-riscv

Updated Mar 27, 2023
VHDL

rodrigomelo9 / verifying-foss-hdl-synthesizers

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a project to check the FOSS synthesizers against vendors EDA tools

vivado ise ghdl yosys iverilog verilator quartus pyfpga ghdl-yosys-plugin foss-synthesizers

Updated Sep 26, 2020
Makefile

umarcor / SIEAV

Sponsor

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Co-simulation and behavioural verification with VHDL, C/C++ and Python/m

matlab octave gtkwave ghdl vunit cosim co-simulation

Updated Mar 23, 2023
VHDL

SalvatoreBarone / CNN-VHDL

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A library of VHDL components for Neural Networks

vhdl artificial-intelligence approximation artificial-neural-networks convolutional-neural-networks ghdl xilinx-fpga lenet-5 approximate-computing approximate-algorithms virtex

Updated Sep 23, 2021
C++

JulyWitch / vhdl_ghdl_examples

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Simple VHDL examples using ghdl as compiler and wave generating

vhdl ghdl vhdl-code scansion vhdl-examples vhdl-testbench gtkwa

Updated Jun 21, 2022
VHDL

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