verilog

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Here are 2,901 public repositories matching this topic...

platformio / platformio-core

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A professional collaborative platform for embedded development 👽

Updated Nov 5, 2022
Python

chipsalliance / chisel3

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Chisel 3: A Modern Hardware Design Language

scala chip-generator chisel rtl chisel3 firrtl verilog

Updated Nov 5, 2022
Scala

logisim-evolution / logisim-evolution

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Digital logic design tool and simulator

education simulator fpga vhdl logic circuits verilog circuit digital-logic logisim digital-circuit digital-circuits timing-diagram digital-logic-design logisim-evolution

Updated Nov 5, 2022
Java

open-sdr / openwifi

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open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

Updated Oct 25, 2022
C

SI-RISCV / e200_opensource

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Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

cpu core verilog china nuclei risc-v ultra-low-power

Updated Mar 24, 2021
Verilog

SpinalHDL / VexRiscv

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A FPGA friendly 32 bit RISC-V CPU implementation

cpu fpga vhdl riscv verilog soc spinalhdl softcore

Updated Oct 27, 2022
Assembly

jbush001 / NyuziProcessor

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GPGPU microprocessor architecture

processor-architecture fpga hardware gpu graphics verilog microprocessor gpu-computing

Updated Sep 11, 2022
C

LeiWang1999 / FPGA

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帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

fpga verilog xilinx vivado pynq

Updated May 15, 2022

darklife / darkriscv

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opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

cpu fpga core processor riscv rtl verilog risc-v rv32i softcore processor-design rv32e

Updated Oct 7, 2022
Verilog

FPGAwars / icestudio

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❄️ Visual editor for open FPGA boards

javascript editor fpga ide blocks verilog icestorm lattice icestudio

Updated Nov 5, 2022
JavaScript

verilator / verilator

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Verilator open-source SystemVerilog simulator and lint system

cpp rtl verilog compilers systemc system-verilog verilator verilog-simulator

Updated Nov 5, 2022
C++

cocotb / cocotb

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cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

python test vhdl verification verilog uvm

Updated Nov 5, 2022
Python

clash-lang / clash-compiler

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Haskell to VHDL/Verilog/SystemVerilog compiler

haskell asic fpga vhdl verilog systemverilog hardware-description-language

Updated Nov 5, 2022
Haskell

SpinalHDL / SpinalHDL

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Scala based HDL

scala fpga vhdl rtl verilog

Updated Nov 5, 2022
Scala

analogdevicesinc / hdl

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HDL libraries and projects

fpga verilog hdl hacktoberfest analog-devices jesd204b

Updated Nov 5, 2022
Verilog

aappleby / MetroBoy

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A repository of gate-level simulators and tools for the original Game Boy.

emulator simulator gameboy gameboy-emulator verilog hdl

Updated Nov 5, 2022
C++

platformio / platformio-vscode-ide

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PlatformIO IDE for VSCode: The next generation integrated development environment for IoT

debugger iot microcontroller embedded fpga hardware vscode platformio verilog

Updated Nov 1, 2022
JavaScript

ZipCPU / zipcpu

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A small, light weight, RISC CPU soft core

cpu fpga verilog cross-compiler wishbone soft-core verilator zipcpu wishbone-bus risc-cpu

Updated Oct 31, 2022
Verilog

olofk / fusesoc

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Package manager and build abstraction tool for FPGA/ASIC development

python package-manager fpga vhdl eda verilog reuse

Updated Oct 31, 2022
Python

olofk / serv

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SERV - The SErial RISC-V CPU

asic fpga verilog risc-v

Updated Oct 25, 2022
Verilog

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