seldridge
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1,638 contributions in the last year
Activity overview
Contributed to
llvm/circt,
chipsalliance/chisel3,
chipsalliance/firrtl-spec
and 21 other
repositories
Contribution activity
February 2023
Created 60 commits in 2 repositories
Created a pull request in chipsalliance/chisel3 that received 2 comments
Convert Scaladoc comment to normal comment, NFC
Change a comment to workaround an unmoored Scaladoc comment error. This is done to workaround an error I started seeing here: https://github.com/ch…
+6
−21
•
2
comments
Opened 33 other pull requests in 2 repositories
chipsalliance/chisel3
28
merged
3
open
- Fix bug in "--split-verilog" output
- Deprecate Protobuf Emission
- Remove SFC Dependencies in AnnotatingDiamondSpec
- Add "--split-verilog" circt.*.ChiselStage option
- Deprecate CIRCTStage (firtool wrapper)
- Remove a FIRRTL phase CIRCTStage "currentState"
- [circt] Remove CIRCTStage optional prereq on SFC
- Deprecate NoRunFirrtlCompilerAnnotation
- Copy chisel3.stage.ChiselStageSpec tests for CIRCT
- Convert tests to circt.stage.ChiselStage
- Pass ChiselCircuitAnnotation through CIRCT phase
- Drop ImportDefinitionAnnotation in CIRCT Phase
- Decouple {circt, chisel3}.stage.ChiselStage
- Deprecate group API
- Deprecate chisel3.stage.ChiselStage
- [circt] Remove reliance on some FIRRTL Phases
- [circt] Stop dropping RunFirrtlTransformAnnotation
- [CIRCT] Remove CombinationalPath Anno Dropping
- [CIRCT] Remove wrong ReplSeqMemAnno to bbox arg
- Convert ExtModuleImplSpec to use MFC
- Convert SelectSpec to use MFC
- Move AnnotationNoDedup Test to MFC
- Convert ForceNamesSpec to use MFC
- Deprecate forceName Component APIs, Transform
- Deprecate loadMemoryFromFile SFC Details
- Some pull requests not shown.
Reviewed 29 pull requests in 3 repositories
llvm/circt
16 pull requests
- [FIRRTL][PortInfo] Add emitError/emitWarning helpers.
- [LowerToHW] Use port locations for diagnostics, don't dump module.
- Unshallow CIRCT clone in uploadBinaries workflow
- [FIRRTL][FoldMemRegs] Fixups to avoid memory safety issues.
- Improve MacOS published binaries and flow
- [FIRRTL] Add a convention attribute to modules
- [FIRRTL][LegacyWiring] Fix insertion point for fieldID.
- [LowerAnnotations] Allow wiring type-equivalent types.
- [CheckCombCycles] Implement an iterative Tarjan's SCC to detect cycles
- [SV][ETC] Name port after instance result name, as well.
- [firtool] Use CIRCT's StripDebInfo pass instead of upstream
- [GC] Update numXMRs statistic.
- [FIRRTL][NFC] Remove unused port boring/LCA methods.
- [ExportVerilog][PrettifyVerilog] Fix exprInEventControl
- [CHIRRTL][NFC] Indicate using new fold API to squelch warnings.
- Bump LLVM to 95e49f5a74c9e79778a62cc58b15875613cf9e59.
chipsalliance/chisel3
11 pull requests
- Bump firtool to 1.32.0
- Give a source line and caret for errors when possible
- first draft of IR/serializer changes
- Add an annotation for specifying module port conventions
- Add "--split-verilog" circt.*.ChiselStage option
- Builder ContextCache
- Deprecate chisel3.stage.ChiselStage
- Bump firtool to 1.30.0
- Use deprecatedMFCMessage in TraceSpec
- Fix BlackBoxImplSpec tests that were still using SFC
- [website] Stop publishing pre 3.5 API docs, clean up deploy flow
chipsalliance/firrtl-spec
2 pull requests
Created an issue in chipsalliance/chisel3 that received 8 comments
MixedVec Doesn't Work with SuggestName
As reported by @oharboe, a MixedVec doesn't seem to work when using the .suggestName to change the name of the numeric identifiers created by the M…
8
comments
Opened 5 other issues in 1 repository
54
contributions
in private repositories
Feb 1 – Feb 25