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vhdl

Here are 2,057 public repositories matching this topic...

logisim-evolution

logisim-evolution / logisim-evolution

Digital logic design tool and simulator

education simulator fpga vhdl logic circuits verilog circuit digital-logic logisim digital-circuit digital-circuits timing-diagram digital-logic-design logisim-evolution

Updated Feb 28, 2023
Java

ghdl / ghdl

VHDL 2008/93/87 simulator

simulator compiler hardware llvm vhdl gcc ghdl hacktoberfest testbench

Updated Mar 6, 2023
VHDL

SpinalHDL / VexRiscv

A FPGA friendly 32 bit RISC-V CPU implementation

cpu fpga vhdl riscv verilog soc spinalhdl softcore

Updated Mar 5, 2023
Assembly

cocotb / cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

python test vhdl verification verilog uvm

Updated Mar 5, 2023
Python

clash-lang / clash-compiler

Haskell to VHDL/Verilog/SystemVerilog compiler

haskell asic fpga vhdl verilog systemverilog hardware-description-language

Updated Mar 6, 2023
Haskell

SpinalHDL / SpinalHDL

Scala based HDL

scala fpga vhdl rtl verilog

Updated Mar 6, 2023
Scala

neorv32

stnolting / neorv32

🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

microcontroller embedded cpu fpga processor vhdl riscv verilog rtos soc risc-v openocd soft-core system-on-chip rv32 neorv32

Updated Mar 5, 2023
VHDL

olofk / fusesoc

Package manager and build abstraction tool for FPGA/ASIC development

python package-manager fpga vhdl eda verilog reuse

Updated Mar 3, 2023
Python

drom / awesome-hdl

Hardware Description Languages

awesome vhdl verilog awesome-list hdl hacktoberfest hardware-description-language

Updated Feb 23, 2023

VUnit / vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

unit-testing asic fpga vhdl verification testbench verilog-hdl systemverilog-hdl universal-verification-methodology

Updated Mar 6, 2023
VHDL

antonblanchard / microwatt

A tiny Open POWER ISA softcore written in VHDL 2008

processor vhdl openpower ppc64le

Updated Feb 20, 2023
Verilog

olofk / edalize

An abstraction library for interfacing EDA tools

Updated Mar 3, 2023
Python

sergeykhbr / riscv_vhdl

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

debugger qt simulator cpu vhdl riscv systemc soc

Updated Feb 17, 2023
Verilog

nickg / nvc

Sponsor

VHDL compiler and simulator

simulator fpga compiler vhdl

Updated Mar 6, 2023
VHDL

VLSI-EDA / PoC

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

Updated Nov 29, 2020
VHDL

open-sdr / openwifi-hw

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

linux fpga zynq hls hardware vhdl rtl verilog xilinx sdr wi-fi analog-devices ieee80211 dma software-defined-radio ofdm csma ad9361 mac80211

Updated Feb 27, 2023
Verilog

JulianKemmerer / PipelineC

A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

python c fpga hls hardware vhdl pipelines open-source-hardware high-level-synthesis hardware-description-language fpga-accelerators fpga-acceleration fpga-programming hardware-description

Updated Mar 4, 2023
Python

TerosTechnology / vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

fpga vhdl verilog systemverilog

Updated Mar 5, 2023
JavaScript

Nuand / bladeRF-wiphy

bladeRF-wiphy is an open-source IEEE 802.11 compatible software defined radio VHDL modem

vhdl rtl hdl ofdm bladerf ofdm-wireless-communications 80211 dsss

Updated Feb 26, 2022
VHDL

howerj / forth-cpu

A Forth CPU and System on a Chip, based on the J1, written in VHDL

c simulator cpu fpga processor vhdl forth target-board softcore

Updated Mar 22, 2022
VHDL

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