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vlsi

Here are 209 public repositories matching this topic...

The-OpenROAD-Project / OpenLane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

magic asic rtl verilog vlsi foundry yosys klayout caravel netgen system-on-chip openroad openram skywater 130nm soc-design rtl2gds

Updated Mar 20, 2023
Verilog

VLSI-EDA / PoC

IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

Updated Nov 29, 2020
VHDL

limbo018 / DREAMPlace

Deep learning toolkit-enabled VLSI placement

deep-learning pytorch gpu-acceleration vlsi vlsi-physical-design vlsi-placement

Updated Mar 20, 2023
C++

OpenTimer / OpenTimer

A High-performance Timing Analysis Tool for VLSI Systems

parallel-computing eda circuit-simulator cad verilog cpp17 circuit-simulation vlsi circuit-analysis computer-aided-design vlsi-physical-design sta electronic-design-automation vlsi-circuits static-timing-analysis

Updated Dec 28, 2022
Verilog

nitram2342 / degate

Open source software for chip reverse engineering.

visualization gui library vhdl reverse-engineering image-processing verilog chip image-recognition vlsi

Updated Sep 22, 2020
C++

Degate

DegateCommunity / Degate

A modern and open-source cross-platform software for chips reverse engineering.

security multi-platform gui cross-platform cpp vhdl reverse-engineering cybersecurity verilog chips vlsi security-tools

Updated Oct 30, 2022
C++

AUCOHL / DFFRAM

Standard Cell Library based Memory Compiler using FF/Latch cells

verilog vlsi vlsi-physical-design vlsi-circuits electronics-design asic-design

Updated Feb 23, 2023
Verilog

antonblanchard / vlsiffra

Create fast and efficient standard cell based adders, multipliers and multiply-adders.

verilog booth vlsi adder multiplier physical-design dadda amaranth-hdl

Updated Mar 18, 2023
Python

purdue-onchip / gds2Para

GDSII File Parsing, IC Layout Analysis, and Parameter Extraction

parse eda vlsi integrated-circuits interconnect gdsii spef electronic-design-automation vlsi-circuits

Updated Mar 17, 2021
C++

asyncvlsi / act

ACT hardware description language and core tools.

language eda circuit-simulator cad dataflow chp dataflow-programming prs hdl vlsi hardware-description-language production-rules design-automation asynchronous-circuits vlsi-cad asynchronous-vlsi communicating-hardware-processes

Updated Mar 17, 2023
C++

EEsim

danchitnis / EEsim

A browser-based SPICE circuit simulator

simulation electronics webassembly wasm spice emscripten circuit vlsi cmos ngspice webgl-plot

Updated Feb 27, 2023
TypeScript

hsluoyz / Atalanta

Sponsor

Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.

verilog vlsi atalanta atpg

Updated Apr 30, 2013
Verilog

varunnagpaal / Digital-Hardware-Modelling

Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)

fpga hls hardware opencl vhdl rtl verilog systemverilog systemc vlsi digital-systems digital-hardware hardware-models

Updated Dec 11, 2020
VHDL

ahmed-agiza / EDAViewer

EDAV: Open-Source EDA Viewer; render design LEF/DEF files in your browser!

Updated Jan 6, 2023
JavaScript

luckyrantanplan / nthu-route

VLSI EDA Global Router

router eda vlsi vlsi-physical-design electronic-design-automation vlsi-circuits globalrouter ispd lattice-graph multi-maze-routing

Updated Jan 22, 2018
C++

OpenTimer / Parser-SPEF

A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

eda circuits cpp17 vlsi computer-aided-design vlsi-physical-design sta spef electronic-design-automation vlsi-circuits parasitic static-timing-analysis

Updated Aug 7, 2022
C++

ieee-ceda-datc / RDF-2019

DATC RDF

routing eda cad vlsi logic-synthesis placement vlsi-physical-design design-automation design-flow vlsi-cad ieee-ceda ieee-ceda-datc vlsi-design-flow clock-tree

Updated Jul 31, 2020
Verilog

asyncvlsi / AMC

AMC: Asynchronous Memory Compiler

eda vlsi design-automation asynchronous-vlsi asynchronous-sram

Updated Jun 29, 2020
Python

leviathanch / qtflow

A Qt5 based free VLSI development tool

Updated Jun 24, 2018
C++

andrsmllr / magic_vlsi_examples

Some simple examples for the Magic VLSI physical chip layout tool.

asic vlsi vlsi-physical-design

Updated Mar 9, 2021

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