sky130

Here are 40 public repositories matching this topic...

efabless / caravel_mpw-one

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

magic yosys caravel picorv32 openroad openram sky130

Updated Feb 22, 2022
Verilog

efabless / caravel

Star

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

magic yosys caravel picorv32 openroad vexriscv openram sky130

Updated Oct 12, 2022
Verilog

google / skywater-pdk-sky130-raw-data

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Raw data collected about the SKY130 process technology.

asic eda spice ic silicon integrated-circuits sky130

Updated Aug 26, 2022
Jupyter Notebook

google / open-source-pdks

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Index of the fully open source process design kits (PDKs) maintained by Google.

asic eda silicon pdk openroad skywater 130nm sky130 180nm globalfoundries gf180mcu

Updated Sep 4, 2022

mattvenn / flipflop_demo

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Flip flop setup, hold & metastability explorer tool

simulation ngspice flip-flop metastability sky130

Updated Jun 11, 2022
Jupyter Notebook

laurentc2 / SKY130_for_KLayout

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KLayout technology files for Skywater SKY130

klayout lvs drc sky130

Updated Jun 12, 2021
Ruby

iic-jku / iic-osic

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JKU IIC environment (tools, examples) for Open-Source IC (OSIC) Design for SKY130.

magic netgen ngspice lvs openlane sky130 xschem

Updated Oct 11, 2022
Shell

ShonTaware / SRAM_SKY130

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Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns

openram sky130 sram-memories

Updated May 2, 2021
SourcePawn

google / skywater-pdk-libs-sky130_fd_bd_sram

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SRAM build space for SKY130 provided by SkyWater.

asic eda sram ic integrated-circuits sky130 silcon

Updated Oct 20, 2021

google / skywater-pdk-libs-sky130_fd_pr

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Primitives for SKY130 provided by SkyWater.

magic asic eda spice ic klayout integrated-circuits ngspice xyce sky130 xschem silcon

Updated Feb 23, 2022

mattvenn / instrumented_adder

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Instrumenting adders to measure speed

asic hardware simulation adder ngspice sky130

Updated Jun 8, 2022
Verilog

google / skywater-pdk-libs-sky130_bag3_pr

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BAG (BAG AMS Generator) Primitives Library for SKY130

analog bag integrated-circuits analog-circuit sky130

Updated Feb 10, 2022
Jupyter Notebook

ShonTaware / OpenSource_Physical_Design

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This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK

open-source vlsi-physical-design sky130 openlane-flow

Updated Feb 22, 2022

google / skywater-pdk-libs-sky130_fd_sc_hd

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"High density" digital standard cells for SKY130 provided by SkyWater.

asic eda ic silicon integrated-circuits openroad sky130 standard-cells

Updated Sep 17, 2022
Verilog

AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop

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Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130

asic vlsi vlsi-physical-design rtl2gds openlane sky130 openlane-flow

Updated Sep 17, 2022

google / skywater-pdk-libs-sky130_fd_sc_ls

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"Low speed" digital standard cells for SKY130 provided by SkyWater.

asic eda ic silicon integrated-circuits openroad sky130 standard-cells

Updated Apr 23, 2021
Verilog

google / skywater-pdk-libs-sky130_fd_io

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IO and periphery cells for SKY130 provided by SkyWater.

asic eda io ic silicon integrated-circuits sky130

Updated Apr 23, 2021

ShonTaware / LowPower

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Various low power labs using sky130

vcs low-power upf sky130

Updated Sep 3, 2021
Verilog

mattvenn / simulate-gate

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Project 1.1 Simulate a Skywater 130nm standard cell using ngspice

asic simulate ngspice sky130

Updated Sep 7, 2022
Makefile

google / skywater-pdk-libs-sky130_fd_sc_lp

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"Low power" digital standard cells for SKY130 provided by SkyWater.

asic eda ic silicon integrated-circuits openroad sky130 standard-cells

Updated Apr 23, 2021
Verilog

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