Here are 38 public repositories matching this topic...

ZipCPU / zipcpu

Star 555

A small, light weight, RISC CPU soft core

cpu fpga verilog cross-compiler wishbone soft-core verilator zipcpu wishbone-bus risc-cpu

• Updated May 19, 2020
• Verilog

ZipCPU / wb2axip

Star 114

Bus bridges and other odds and ends

fpga gplv3 xilinx wishbone xilinx-vivado wishbone-bus axi-bus

• Updated Jul 2, 2020
• Verilog

ZipCPU / wbuart32

Star 105

A simple, basic, formally verified UART controller

fpga verilog uart serialport uart-verilog wishbone verilator wishbone-bus

• Updated Jun 9, 2020
• Verilog

ZipCPU / autofpga

Star 93

A utility for Composing FPGA designs from Peripherals

c-plus-plus fpga verilog wishbone verilator wishbone-bus

• Updated Jul 2, 2020
• C++

ZipCPU / openarty

Star 77

An Open Source configuration of the Arty platform

fpga fpga-soc wishbone verilator arty zipcpu wishbone-bus

• Updated Jul 1, 2020
• Verilog

ZipCPU / wbscope

Star 41

A wishbone controlled scope for FPGA's

fpga verilog debugging-tools wishbone verilator wishbone-bus

• Updated Jun 11, 2020
• Verilog

ZipCPU / sdspi

Star 38

SD-Card controller, using a SPI interface that is (optionally) shared

spi-interface fpga verilog sd-card wishbone verilog-components verilator wishbone-bus sd-interface

• Updated Jan 23, 2020
• Coq

ZipCPU / s6soc

Star 26

CMod-S6 SoC

fpga fpga-soc wishbone verilator zipcpu wishbone-bus

• Updated Jan 6, 2018
• Verilog

lxp32 / lxp32-cpu

Star 20

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

cpu fpga vhdl risc wishbone soft-core risc-processor wishbone-bus risc-cpu

• Updated Feb 25, 2019
• Assembly

ZipCPU / dbgbus

Star 17

A collection of debugging busses developed and presented at zipcpu.com

verilog debugging-tools wishbone fgpa verilator wishbone-bus

• Updated Apr 2, 2020
• Verilog

ZipCPU / wbfmtx

Star 12

A wishbone controlled FM transmitter hack

fpga hack verilog wishbone verilog-components wishbone-bus fm-transmitter

• Updated Nov 25, 2019
• Verilog

bnossum / midgetv

Star 4

RV32I for iCE40 in less than 400 SB_LUT4s. Wishbone interface.

riscv verilog lattice microcode yosys ice40 wishbone rv32i verilator ice40up5k upduino2 iceblink40-hx1k

• Updated Jan 5, 2020
• C

ZipCPU / wbicapetwo

Star 3

Wishbone to ICAPE interface conversion

fpga gplv3 xilinx wishbone verilator iprog-command

• Updated Mar 18, 2020
• Verilog

hotwolf / WbXbc

Star 2

HDL components to build a customized Wishbone crossbar switch

verilog hdl wishbone crossbar

• Updated May 30, 2019
• SystemVerilog

semahawk / wishbone

Star 1

Trying to learn Wishbone by implementing few master/slave devices

verilog verilog-hdl wishbone wishbone-bus

• Updated Jan 7, 2019
• SystemVerilog

wishbone-modules / wishbone-output-elasticsearch

Star 1

A Wishbone output module to write data to the Elasticsearch document store

python microservices event-processing wishbone

• Updated Jul 28, 2018
• Python

PacoReinaCampo / MPSoC-DMA

Star 1

Direct Access Memory for MPSoC

wishbone ahb3-lite

• Updated Jul 1, 2020
• SystemVerilog

semahawk / icarium

Star 1

Trying to implement a soft core SoC

verilog verilog-hdl wishbone soft-core system-on-chip softcore wishbone-bus

• Updated Apr 6, 2019
• Verilog

PacoReinaCampo / MPSoC-MPI

Star 1

Message Passing Interface for MPSoC

wishbone ahb3-lite

• Updated Jul 1, 2020
• SystemVerilog

PacoReinaCampo / MPSoC-MSI

Star 1

Master Slave Interface for MPSoC

wishbone ahb3-lite

• Updated Jul 1, 2020
• SystemVerilog

PacoReinaCampo / MPSoC-GPIO

Star 1

General Purpose Input Output for MPSoC

wishbone ahb3-lite

• Updated Jul 1, 2020
• SystemVerilog

batuhanates / ibex_wb

Star 1

RISC-V Ibex core with Wishbone B4 interface

fpga riscv wishbone ibex

• Updated Apr 26, 2020
• C

PacoReinaCampo / MPSoC-SPRAM

Star 1

Single-Port RAM for Instruction & Data for MPSoC

wishbone ahb3-lite

• Updated Jul 1, 2020
• SystemVerilog

PacoReinaCampo / MPSoC-DBG

Star 1

Debugger on Chip for MPSoC

wishbone ahb3-lite

• Updated Jul 1, 2020
• SystemVerilog

PacoReinaCampo / MPSoC-MPRAM

Star 1

Multi-Port RAM for Instruction & Data for MPSoC

wishbone ahb3-lite

• Updated Jul 1, 2020
• SystemVerilog

PacoReinaCampo / MPSoC-UART

Star 1

Universal Asynchronous Receiver-Transmitter for MPSoC

wishbone ahb3-lite

• Updated Jul 1, 2020
• SystemVerilog

pbing / Wishbone

Star 0

Check Wishbone B4 variants

systemverilog wishbone wishbone-bus

• Updated Aug 30, 2018
• SystemVerilog

zz-systems / Plasma-SoC

Star 0

Plasma MIPS (I) SoC

cpu mips de1-soc zedboard wishbone system-on-chip wishbone-bus

• Updated Sep 17, 2018
• C

wishbone-modules / wishbone-input-azure_queue_storage

Star 0

A wishbone input module to consume messages from Azure queue storage

microservices azure event-processing queues wishbone

• Updated Mar 31, 2018
• Python

EnricoRuggiano / stm32-watchdogs

Star 0

stm32 watchdog system-verilog wishbone hardware-description-language

• Updated Jan 25, 2019
• SystemVerilog

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