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ice40
Here are 59 public repositories matching this topic...
Open source ultrasound processing modules and building blocks
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Jul 26, 2020 - Jupyter Notebook
An attempt at a small Verilog implementation of the original Apple 1 on an FPGA
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Jul 30, 2020 - Verilog
Small Processing Unit 32: A compact RV32I CPU written in Verilog
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Aug 24, 2020 - C
A collection of little open source FPGA hobby projects
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Feb 6, 2020 - SystemVerilog
iCEstick iCE40-HX1K FPGA hacks ~ iCEfm FM Transmitter
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Aug 11, 2017 - Verilog
FGBA-based LPC bus sniffing tool for Lattice iCEstick Evaluation Kit
security
fpga
attack
tool
sniffer
lpc
security-vulnerability
sniffing
it-security
ice40
icestick
security-tools
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Jun 9, 2020 - Verilog
IP operations in verilog (simulation and implementation on ice40)
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Oct 24, 2019 - Verilog
Simple voltage glitcher implementation for the Lattice iCEstick Evaluation Kit
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Jan 30, 2020 - Verilog
Upload a FPGA ice40 bitstream via curl using a ESP32 in arduino
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Updated
Mar 3, 2018 - C
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Vendor tools dram tests were not enabled until #1234 got merged.
With SymbiFlow/symbiflow-arch-defs#1268 I have temporarily disabled the vivado_targets, to let CI go green (as it has been red for too long now).
This issue is to keep track of the problem with DRAM evaluated on vendor tools with fasm2bels.