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yosys

Here are 46 public repositories matching this topic...

m-labs / nmigen

Star

A refreshed Python toolbox for building complex digital hardware

fpga hdl yosys nmigen

Updated Aug 19, 2020
Python

nturley / netlistsvg

Star

draws an SVG schematic from a JSON netlist

visualization diagram elk yosys klayjs netlist

Updated May 31, 2020
JavaScript

nmigen / nmigen

Star

A refreshed Python toolbox for building complex digital hardware

fpga hdl yosys nmigen

Updated Sep 4, 2020
Python

olofk / edalize

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An abstraction library for interfacing EDA tools

Updated Sep 8, 2020
Python

efabless / openlane

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OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Updated Sep 11, 2020
Verilog

zachjs / sv2v

Star

SystemVerilog to Verilog conversion

conversion verilog systemverilog yosys

Updated Aug 21, 2020
Haskell

forflo / yodl

Star

A VHDL frontend for Yosys

Updated Feb 27, 2017
C++

scarv / xcrypto

Star

XCrypto: a cryptographic ISE for RISC-V

open-source cryptography cpu crypto hardware riscv verilog research-project mit-license ise icarus-verilog hardware-acceleration formal-verification yosys instruction-set-architecture risc-v xcrypto

Updated Aug 17, 2020
Verilog

dadamachines / doppler

Star

Arduino compatible – Cortex M4F & FPGA Development Board

arduino fpga icestorm yosys ice40 ice40up5k samd51

Updated Mar 22, 2019

mattvenn / fpga-sdft

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sliding DFT for FPGA, targetting Lattice ICE40 1k

fpga verilog fourier fft icestorm yosys sdft

Updated Apr 24, 2020
Verilog

mmicko / enigmaFPGA

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Enigma in FPGA

fpga verilog yosys ice40 blackice goboard

Updated May 18, 2019
Verilog

ghdl / docker

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Scripts to build and use docker images

dockerfiles hardware ci simulation vhdl actions verilog synthesis icestorm gtkwave ghdl testbench vunit yosys openocd pnr nextpnr prjtrellis

Updated Aug 31, 2020
Shell

fpga-tool-perf

SymbiFlow / fpga-tool-perf

Star

Open

Add daveshah1's gameboy up5k-demo

mithro commented Aug 8, 2018

@daveshah1 has some pretty nice up5k demos at https://github.com/daveshah1/up5k-demos/tree/master

As we really care about the up5k, it seems like a good idea to add these demos to the perf tool.

Read more

enhancement good first issue

Open

Add daveshah1's nes up5k-demo

tmeissner / psl_with_ghdl

Star

Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

vhdl assertions ghdl formal-verification yosys psl symbiyosys functional-coverage

Updated Jun 27, 2020
VHDL

YosysHQ / padring

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A padring generator for ASICs

asic eda chip vlsi yosys

Updated Jul 14, 2020
C++

rodrigomelo9 / verifying-foss-hdl-synthesizers

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a project to check the FOSS synthesizers against vendors EDA tools

vivado ise ghdl yosys iverilog verilator quartus pyfpga ghdl-yosys-plugin foss-synthesizers

Updated May 18, 2020
Makefile

YoWASP / yosys

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Unofficial Yosys WebAssembly packages

python fpga pypi webassembly yosys

Updated Sep 12, 2020
Python

tmeissner / formal_hw_verification

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Trying to verify Verilog/VHDL designs with formal methods and tools

vhdl verilog systemverilog ghdl formal-verification yosys psl symbiyosys

Updated Aug 10, 2020
VHDL

risc8

osresearch / risc8

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Mostly AVR compatible FPGA soft-core

microcontroller fpga yosys ice40 softcore upduino up5k

Updated Jul 31, 2020
Coq

sphinxcontrib-verilog-diagrams

SymbiFlow / sphinxcontrib-verilog-diagrams

Star

Sphinx Extension which generates various types of diagrams from Verilog code.

documentation fpga sphinx documentation-tool rtl verilog diagrams hdl yosys sphinx-extension symbiflow

Updated Sep 11, 2020
Python

dadamachines / doppler-FPGA-firmware

Star

Bitstream src for doppler

docker dsp icestorm yosys risc-v ice40 i2s-audio ice40up5k

Updated Apr 12, 2019
C

SymbiFlow / ibex-yosys-build

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Testing Ibex build using Yosys and open source toolchains.

riscv yosys risc-v ibex

Updated Sep 9, 2020
Shell

anuejn / XC9500

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WIP open source tooling for the XC9500 / XC9500XL series of CPLDs from Xilinx.

reverse-engineering digital-logic yosys cpld

Updated Aug 21, 2020
Python

scarv / scarv-cpu

Star

SCARV: a side-channel hardened RISC-V platform

open-source cryptography cpu crypto riscv verilog research-project mit-license ise formal-verification yosys instruction-set-architecture verilator riscv32 xcrypto

Updated Sep 11, 2020
Verilog

porglezomp / nangate

Star

Yosys passes to syntheize to NaN gates (à la http://tom7.org/nand/)

verilog logic-synthesis yosys yosys-plugin nan-gate

Updated Apr 26, 2019
C++

ArsenioDev / EasyFPGAToolsInstall

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An EASY way to install the various Open FPGA Toolchain flavors in one command

fpga icestorm yosys ice40 ecp5 prjtrellis

Updated Apr 30, 2020
Shell

yosys-symbiflow-plugins

SymbiFlow / yosys-symbiflow-plugins

Star

Plugins for Yosys developed as part of the SymbiFlow project.

toolchain fpga eda xilinx yosys xilinx-fpga symbiflow yosys-plugin

Updated Sep 11, 2020
Verilog

GuzTech / verilog_ips

Star

Various IPs implemented in Verilog

fpga hardware verilog formal-verification yosys

Updated Feb 17, 2019
SystemVerilog

DoctorWkt / ULX3S-Blinky

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A blinky project for the ULX3S v3.0.3 FPGA board

fpga verilog yosys nextpnr prjtrellis

Updated Feb 16, 2019
Verilog

scarv / xcrypto-ref

Star

XCrypto: a cryptographic ISE for RISC-V

cryptography hardware riscv verilog ise formal-verification yosys risc-v

Updated Jun 27, 2019
Verilog

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