Type of issue: other enhancement

Impact: no functional change

Development Phase: request

Other information
This is more a meta-issue mostly related to the beginners user experience. I think most of these issues are not done by more experienced devs.

If the current behavior is a bug, please provide the steps to reproduce the problem:

1. Start with [chisel-templat

If TOPLEVEL is not set iverilog fails with an obscure error message because there is nothing after the -s option. I recommend that Makefile.sim check for TOPLEVEL and (and other required variables) and give a clean error message.

EH1 has a lot of examples where a sequent CFunc contains only a handful ot statements (often 1 or 2) and is called only once. This causes a performance penalty when --output-split puts these in a different function than _eval and hence the compiler can't inline them, so we should inline these ourselve when it's obviously the right thing to do.

Tuo Xie requested the ability to visualize clocking (pins & wires I believe). We should make it easier to visualize subsets of the device routing resource and types of routing nets.

Proposed Behaviour

Add filtering to the rr_nodes displayed (ToggleRR), and to the nets displayed (ToggleNets). I think we should have an option to filter what is shown by node type, node name (segment or pin t