CHIPS Alliance
Common Hardware for Interfaces, Processors and Systems
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- sv-tests-results
Output of the sv-tests runs.
- UHDM
Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
- rocket-chip
Rocket Chip Generator