mor1kx - an OpenRISC 1000 processor IP core
Verilog 402 136
Forked from bandvig/or1k_marocchino
OpenRISC processor IP core based on Tomasulo algorithm
Verilog 21 7
Misc documentation and specifications
6 9
Linux kernel source tree
The OpenRISC 1000 architectural simulator
Source for openrisc.io
GCC port for OpenRISC 1000
newlib OpenRISC development
Unified OpenRISC 1000 test suite
Binutils and gdb fork for OpenRISC
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